Regviz

NXP Semiconductors /LPC43xx /CREG /CREG5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CREG5

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC43xx/CREG/CREG5#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (NO_EFFECT)M0SUBTAPSEL 0 (NO_EFFECT)M4TAPSEL 0 (NO_EFFECT)M0APPTAPSEL 0RESERVED

M4TAPSEL=NO_EFFECT, M0APPTAPSEL=NO_EFFECT, M0SUBTAPSEL=NO_EFFECT

Description

Chip configuration register 5. Controls JTAG access.

Fields

RESERVED

Reserved.
M0SUBTAPSEL

JTAG debug disable for M0SUB co-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.

0 (NO_EFFECT): No effect.

1 (DISABLE_JTAG_DEBUG): Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.
M4TAPSEL

JTAG debug disable for M4 main processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.

0 (NO_EFFECT): No effect.

1 (DISABLE_JTAG_DEBUG): Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.
M0APPTAPSEL

JTAG debug disable for M0APPco-processor. If this bit is set to 1, it can be changed to 0 only through a chip reset.

0 (NO_EFFECT): No effect.

1 (DISABLE_JTAG_DEBUG): Disable JTAG debug. Once JTAG is disabled, JTAG access remains disabled until the chip is reset by any source.
RESERVED

Reserved.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data